A Chaotic Time-Delay Sampled-Data System and Its Implementation

Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. Circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using Flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. Chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes relatively simple structure compared to other chaotic time-delay systems and overcome the complexity of the circuit implementation of the time-delay block.